Aufbau und Nutzung von FPGAs/display

Dieses Modul steuert das 7-segment Display an

`timescale 1ns / 1ps

module display(clk, Z1, Z2, Z3, Z4, segment, ziffer_on); 

    input clk;
    input [3:0] Z1;
    input [3:0] Z2;
    input [3:0] Z3;
    input [3:0] Z4;
    output reg[6:0] segment;
    output reg[0:3] ziffer_on; 
 
	reg signed [13:0] time_stelle = 0;
//	reg signed [2:0] time_stelle = 0;
	reg signed [1:0] stelle = 0; 
	reg signed [3:0] segment_i;


// Zeit bis zum Stellenwechsel
always @ (posedge clk)
begin
time_stelle <= time_stelle + 1;
if (time_stelle == 0)
	stelle <= stelle + 1;
end
 

// Multiplexer zum einschalten der Stelle
always @ *
case (stelle)
2'd0: ziffer_on = 4'b0111;
2'd1: ziffer_on = 4'b1011;
2'd2: ziffer_on = 4'b1101;
2'd3: ziffer_on = 4'b1110;
endcase

always @ *
case (stelle)
2'd0: segment_i = Z1;
2'd1: segment_i = Z2;
2'd2: segment_i = Z3;
2'd3: segment_i = Z4;
endcase

   always @(segment_i)
      case (segment_i)
          4'b0001 : segment = 7'b1111001;   // 1
          4'b0010 : segment = 7'b0100100;   // 2
          4'b0011 : segment = 7'b0110000;   // 3
          4'b0100 : segment = 7'b0011001;   // 4
          4'b0101 : segment = 7'b0010010;   // 5
          4'b0110 : segment = 7'b0000010;   // 6
          4'b0111 : segment = 7'b1111000;   // 7
          4'b1000 : segment = 7'b0000000;   // 8
          4'b1001 : segment = 7'b0010000;   // 9
          4'b1010 : segment = 7'b0001000;   // A
          4'b1011 : segment = 7'b0000011;   // b
          4'b1100 : segment = 7'b1000110;   // C
          4'b1101 : segment = 7'b0100001;   // d
          4'b1110 : segment = 7'b0000110;   // E
          4'b1111 : segment = 7'b0001110;   // F
          default : segment = 7'b1000000;   // 0
      endcase


//assign segment = segment_i;

endmodule