Aufbau und Nutzung von FPGAs/entprellen

Dieses Modul entprellt eine Taste

`timescale 1ns / 1ps

module debounce(clk, in, out);
    input clk;
    input in;
    output reg out;
 
  reg signed [5:0]counter = 0;
  reg in2;
  
 always @ (posedge clk) begin
 
 if (in2 == 1) begin
	if (counter != 6) 
		counter <= counter + 1;
		end
 else 
	if (counter != 0)
		counter <= counter - 1;

	if (counter == 6)
		out <= 1;
	else
		if (counter == 0)
		 out <= 0;
end

always @ (posedge clk)
 in2 <= in;

endmodule